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PRELIMINARY DATA SHEET
SKY73100: 865-960 MHz High Performance VCO/Synthesizer With Integrated Switch
Applications
* 2G, 2.5G, and 3G base station transceivers: - GSM, EDGE, CDMA, WCDMA * General purpose RF systems
Description
Skyworks SKY73100 Voltage-Controlled Oscillator (VCO)/Synthesizer is a fully integrated, high performance signal source for high dynamic range transceivers. The device provides ultra-fine frequency resolution, fast switching speed, and low phase noise performance for 2G, 2.5G, and 3G base station transceivers. The SKY73100 VCO/Synthesizer is a key building block for highperformance radio system designs that require low power and a fine step size. Reference clock generators with an output frequency up to 52 MHz can be used with the SKY73100. The input clock frequency is divided down by programmable dividers (1 to 8) for the synthesizer. The phase detector can operate at a maximum speed of 26 MHz, which allows better phase noise due to the lower division value. The SKY73100 VCO/Synthesizer is provided in a compact, 38-pin Multi-Chip Module (MCM). The device package and pinout are shown in Figure 1. A functional block diagram is shown in Figure 2. Signal pin assignments and functional pin descriptions are provided in Table 1.
Features
* Wideband frequency operation: 865 to 960 MHz * Process-tolerant compensation for VCO * 24-bit fractional-N synthesizer * Ultra-fine frequency resolution of 0.001 ppm * Flexible reference frequency selection * Three-wire serial interface up to 20 MHz clock frequency * Integrated PLL supply regulation for spur isolation * MCM (38-pin, 9 x 12 mm) Pb-free free (MSL3, 260 C per JEDEC J-STD-020) SMT package Skyworks offers lead (Pb)-free, RoHS (Restriction of Hazardous Substances) compliant packaging.
GND
GND
GND
GND
GND
GND
31
38
37
36
35
34
33
32
30 29 28 27 26 25 24 23 22 21 20
GND GND GND SW_EN GND GND GND GND GND RF_OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND
GND GND N/C GND GND GND FREF LD N/C GND
19
VDD
GND
GND
N/C
N/C
CLK
DATA
GND
GND
GND
LE
S958
Figure 1. SKY73100 Pinout- 38-Pin MCM Package (Top View)
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PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
Varactor
Vtune
Lr Cal Lr 2 2 2 Buffer
VCO Out + VCO Out -
Z = 1:4
RF Output SW_EN
SR Out + 7 2 SR Out -
Vtune cap [6:0] Flag
PLL Low Pass Filter 3-Wire Serial Interface CLK LE DAT
R1
SP1
SC1
CPO RF
FREF
R1 Divider
RF PFD
RF Charge Pump N PS
RFIN
7 Mux (LD/Test) N Divider FN ME Divide-by-2 P/P+1 Prescaler
RFINB LD
Modulator
Digital Coarse Calibration
cap [6:0] 7 Calibration Complete
S1040
Figure 2. SKY73100 Functional Block Diagram
Table 1. SKY73100 Signal Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 GND GND GND SW_EN GND GND GND GND GND RF_OUT GND GND GND N/C GND GND CLK DATA LE Name Ground Ground Ground Synthesizer RF output switch enable Ground Ground Ground Ground Ground Synthesizer output Ground Ground Ground No connection Ground Ground Serial port clock Serial port data Serial port latch enable Description Pin # 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 GND N/C LD FREF GND GND GND N/C GND GND GND GND GND N/C GND GND GND VDD GND Name Ground No connection Lock detect output Frequency reference input Ground Ground Ground No connection Ground Ground Ground Ground Ground No connection Ground Ground Ground +5 V power supply Ground Description
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PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
Technical Description
The SKY73100 is a fractional-N frequency synthesizer using a modulation technique. The fractional-N implementation provides low in-band noise by having a low division and fast frequency settling time. The device also provides programmable, arbitrary fine frequency resolution. This compensates the frequency synthesizer for crystal frequency drift. Serial I/O Control Interface The SKY73100 is programmed through a three-wire serial bus control interface using four 26-bit words. The three-wire interface consists of three signals: CLK (pin 17), LE (pin 19), and the bit serial data line DATA (pin 18). The convention is to load data from the most significant bit to the least significant bit (MSB to LSB). A serial data input timing diagram is shown in Figure 3. Preset timing parameter values are provided in Table 2. Figure 4 depicts the serial bus, which consists of one 26-bit load register and four separate 24-bit registers. Data is initially clocked into the load register starting with the MSB and ending with the LSB. The LE signal is used to gate the clock to the load register, requiring the LE signal to be brought low before the data load. Data is shifted on the rising edge of CLK.
The two final LSBs are decoded to determine which holding register should latch the data. The falling edge of LE latches the data into the appropriate holding register. This programming sequence must be repeated to fill all four holding registers. Loading new data into a holding register not associated with the synthesizer frequency programming does not reset or change the synthesizer. The synthesizer should not lose lock before, during, or after a new serial word load that does not change the programmed frequency. VCO Tuning Loop A VCO auto-tuning loop provides the proper 7-bit coarse tuning setting for the VCO switch capacitors in the VCO output. This sets the oscillation frequency as close to target as possible before starting fine analog tuning. The auto-tuning loop is designed to compensate process variation so that the VCO fine tuning range can be reduced to cover temperature variation only. It significantly reduces VCO gain (Kv) which reduces VCO phase noise.
DATA tDHD tDSU CLK tCLE tLEC tLEW LE
S1053
tCKH tCKL
Figure 3. SKY73100 Serial Data Input Timing Diagram (MSB First)
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PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
Table 2. CLK, DATA, LE Preset Timing Parameters
Parameter Input high voltage (VIH) Input low voltage (VIL) Input current (lDIG) Clock frequency Clock high (tCKH) Clock low (tCKL) Data set up (tDSU) Data hold (tDHD) Clock to latch enable (tCLE) Latch enable width (tLEW) Latch enable to clock (tLEC) Word length Number of words Current drain 1.6 V 0.3 V 1 A (maximum) 15 MHz (maximum) 15 ns (minimum) 15 ns (minimum) 20 ns (minimum) 10 ns (minimum) 20 ns (minimum) 15 ns (minimum) 15 ns (minimum) 26 bits 4 2 A Value
Power-On Preset CLK DATA
(Words 0-3, bits [25:0])
Load Register
Bits [25:2]
Operation Mode Register
Latch
Word 0 Bits [25:2]
Auto Calibration Control Register
Latch
Word 1 Bits [25:2] Frequency
Word 2 Bits [25:2]
Control 1 Register
Latch
Frequency Control 2 Register
Latch
Word 3 Bits [25:2]
Words 0-3 Bits [1:0]
LE
2 LSB Decode (Register Address, Bits [1:0])
S918
Figure 4. Serial Bus Block Diagram
VCO Prescalers The VCO prescalers divide the VCO output signal by either 16/17 or 8/9. The modulator determines whether to divide by 16 or 17 in the 16/17 mode, or whether to divide by 8 or 9 in the 8/9 mode. N-Counter The N-counter consists of two asynchronous ripple counters, a 6-bit M-counter and a 4-bit A-counter. The M-counter determines the counts using the lower division ratio in the prescaler (8 or 16); the A-counter determines the counts using the upper division ratio (9 or 17). By changing the counter setting at each reference clock cycle, the Modulated Fractional Divider (MFD) achieves the desired noise shaping.
VCO MFD Block The MFD block divides down the prescaler output to the Phase Locked Loop (PLL) reference frequency. A third order cascaded modulation technique minimizes spurs through randomization of the division ratio. The MFD block controls the division ratio by dynamically programming the M and A counters in the N-counter. Phase Detector and Charge Pump The phase detector and charge pump detect and integrate the phase and frequency errors of the divided down VCO output versus the reference clock. This results in a feedback adjustment of the control voltage for the VCO.
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PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
Lock Detect Lock detection circuitry provides a CMOS logic level indication when the PLL is frequency locked (high when locked). Reference Input Divider The R-counter (reference input clock divider) consists of three divide-by-two blocks and one multiplexer controlled by the RDIV[1:0] parameter in Legacy Word 2. The R-counter is used to select a divide-by-one to a divide-by-eight function. Synthesizer Output Switch An on-chip switch is integrated into the SKY73100 RF output after the balun and is controlled by the SW_EN signal (pin 4) as indicated below:
SW_EN Input High Low Synthesizer Output On Off
Nactual = Mactual x P + Aactual If: M = Mactual (binary number, fit to six bits) A = Aactual (binary number, fit to four bits) Then: N = M x 24 + A Where: N is the number to be programmed into the N-counter.
(3)
The synthesizer has a selectable prescaler of 8/9 or 16/17. If the 16/17 prescaler is used: P = 24 = 16 In this case, N is the same as Nactual, M is equal to the six MSBs of Nactual, and A is equal to the four LSBs of Nactual. If the 8/9 prescaler is used: P=8 Here, N is not equal to Nactual. The A-counter portion only uses the three LSBs (the 4th bit of the A-counter is a "don't care" bit). The fractional divisor code (FN) sets the fractional-N modulo up to 256 modulo according to the following equation:
1 1 1 FN actual = D7 + D6 2 + D5 3 + 2 2 2
***
The switch provides >50 dB isolation at the synthesizer RF output. This allows the SKY73100 to be used for GSM applications. Synthesizer Programming To program the synthesizer to the correct frequency, values for the N-counter (both M and A portions), fractional divisor (FN), and fractional modulus extender (ME) are needed. These values are used to determine the total divider ratio, DTotal, according to Equation 1: DTotal = Nactual + FNactual + MEactual + 3.5 Where: Nactual = the actual value of the N-counter FNactual = the actual fractional divisor MEactual = the actual fractional modulus extender Because of the way the modulator is implemented in the SKY73103, the number 3.5 must be added to the division number to obtain the final division ratio. The calculated value for DTotal can then be used to determine the correct synthesizer frequency, RF:
RF = FREF x DTotal R1
1 + D0 8 2
(4)
The value of FN is equal to the binary representation of 256 (or 28) x FNactual, or: FN = D7 x 27 + D6 x 26 + D5 x 25+ . . . D0 The fractional modulo can be extended up to 223 using the modulo extender (ME) if required: MEactual = D14(1/29) + D13(1/210) + D12(1/211) + . . . + D0(1/223) The value of ME is equal to the binary representation of the integer part of 223 x MEactual, or: ME = D14 x 214 + D13 x 213 + D12 x 212 + . . .D0 Example 1: A desired synthesizer frequency of 2640.45 MHz is required using a crystal frequency of 16 MHz and a 16/17 prescaler. Since the maximum internal reference frequency is 25 MHz, the crystal frequency does not need to be divided. However, a reference divider ratio of 2 is used for this example. Restating Equation 2 as a function of DTotal: DTotal = (2640.45 x 2)/16 = 330.05625 Where: RF = 2640.45 R1 = 2 FREF = 16 Determine Nactual by subtracting 3.5 from DTotal and removing the fractional portion:
(1)
(2)
Where: FREF = the reference frequency R1 = the reference divider radio The 6-bit M-counter and the 4-bit A-counter portions of the Ncounter are calculated according to the following relationships: Nactual is the actual N-counter value and is the integer portion of (DTotal - 3.5):
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PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
DTotal - 3.5 = 326.55625 Using Equation 3: Nactual = 326 = Mactual x P + Aactual Where: Mactual = 20 P = 16 Aactual = 6 M = Mactual = 20 = 010100b (the six MSBs) A = Aactual = 6 = 0110b (the four LSBs) N = M x 2 + A = 0101000110b (this is the same as Nactual)
4
Using Equation 3: Nactual = 108 = Mactual x P + Aactual Where: Mactual = 13 P=8 Aactual = 4 M = Mactual = 13 = 001101b (the six MSBs) A = Aactual = 4 = 0100b (the four LSBs) N = M x 24 + A = 0011010100b (the value programmed) Multiply the fractional portion that was removed in the previous step by 256 and remove the fractional portion of the result to determine FN: 0.038461538 x 256 = 9.846153728 FN = 9 = 00001001b Divide FN by 256 to determine the actual fractional part, FNactual: FNactual = 9/256 = 0.03515625 Subtract this result from the fractional portion of (DTotal - 3.5) to determine the actual fractional modulus extender, MEactual: MEactual = (DTotal - 3.5 - Nactual) - FNactual = 0.038461538 - 0.03515625 = 0.003305288 Multiply this result by 8388608 (the 23-bit modulator value, 223) and remove the fractional portion to determine the value of ME: 0. 003305288 x 8388608 = 27726.7653 ME = 27726 = 110110001001110b
Multiply the fractional portion that was removed in the previous step by 256 and remove the fractional portion of the result to determine FN: 0.55625 x 256 = 142.4 FN = 142 = 10001110b Divide FN by 256 to determine the actual fractional part, FNactual: FNactual = 142/256 = 0.5546875 Subtract this result from the fractional portion of (DTotal - 3.5) to determine the actual fractional modulus extender, MEactual: MEactual = (DTotal - 3.5 - Nactual) - FNactual = 0.55625 - 0.5546875 = 0.0015625 Multiply this result by 8388608 (the 23-bit modulator value, 223) and remove the fractional portion to determine the value of ME: 0.0015625 x 8388608 = 13107.2 ME = 13107 = 011001100110011b Example 2: A desired synthesizer frequency of 725 MHz is required using a crystal frequency of 13 MHz and an 8/9 prescaler. Since the maximum internal reference frequency is 25 MHz, the crystal frequency does not need to be divided. However, a reference divider ratio of 2 is used for this example. Restating Equation 2 as a function of DTotal: DTotal = (725 x 2)/13 = 111.538461538 Where: RF = 725 R1 = 2 FREF = 13 Determine Nactual by subtracting 3.5 from DTotal and removing the fractional portion: DTotal - 3.5 = 108.038461538
Package and Handling Information
Since the device package is sensitive to moisture absorption, it is baked and vacuum packed before shipping. Instructions on the shipping container label regarding exposure to moisture after the container seal is broken must be followed. Otherwise, problems related to moisture absorption may occur when the part is subjected to high temperature during solder assembly. The SKY73100 is rated to Moisture Sensitivity Level 3 (MSL3) at 260 C. It can be used for lead or lead-free soldering. For additional information, refer to Skyworks Application Note, PCB Design and SMT Assembly/Rework Guidelines for MCM-L Packages, document number 101752. Care must be taken when attaching this product, whether it is done manually or in a production solder reflow environment. Production quantities of this product are shipped in a standard
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PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
tape and reel format. For packaging details, refer to the Skyworks Application Note, Tape and Reel, document number 101568.
Electrical and Mechanical Specifications
The absolute maximum ratings of the SKY73100 are provided in Table 3. The recommended operating conditions are specified in Table 4 and electrical specifications are provided in Table 5. Spur suppression measurements are provided in Table 6. Measurement plots for single sideband phase noise and settling time are shown in Figures 5 and 6, respectively. A typical application schematic for the SKY73100 is provided in Figure 7. Figure 8 shows the package dimensions for the 38-pin MCM and Figure 9 provides the tape and reel dimensions.
Circuit Design Considerations
The following design considerations are general in nature and must be followed regardless of final use or configuration 1. Paths to ground should be made as short and as low impedance as possible. 2. The ground pad of the SKY73100 provides critical electrical grounding requirements. Design the connection to the ground pad to provide the best electrical connection to the circuit board. Multiple vias to the grounding layer are recommended to connect the top layer ground area to the main ground layer. 3. Skyworks recommends including external bypass capacitors on the VDD voltage input (pin 37) of the device. These capacitors should be placed as close as possible to the VDD input pin. 4. A 50 impedance trace is needed for the RF_OUT (pin 10) line.
Electrostatic Discharge (ESD) Sensitivity
The SKY73100 ESD threshold level is 2500 VDC using Human Body Model (HBM) testing. This level applies to RF signal lines >100 MHz, analog and RF lines <100 MHz, digital lines, power supply lines, and ground pins. To avoid latent or visible ESD damage, always follow proper ESD handling precautions.
Table 3. SKY73100 Absolute Maximum Ratings (Note 1)
Parameter Supply voltage Operating temperature, full performance Storage temperature VCC TOP TST Symbol Min 0 -40 -40 Typical Max 5.5 +85 +150 Units V C C
Note 1: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other parameters set at or below their nominal values.
Table 4. SKY73100 Recommended Operating Conditions
Parameter Supply voltage Input voltage (CLK, DATA, LE): Low level High level Output voltage (LD) with 18 k load from VCC PLL: Low level, unlocked High level, unlocked Reference frequency input voltage (FREF, pin 23) Load connected to RF output RF output switch enable: High Low SWENH SWENL 2.2 0.8 FREFIN VCC Symbol Min 4.75 Typical 5.00 Max 5.25 0.6 1.4 Units V V V
0.4 2.4 0.5 1.0 1.5
V V Vp-p
50 , maximum VSWR (load input) 2.0:1, all phases V V
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PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
Table 5. SKY73100 Electrical Characteristics (Note 1) (VCC = 5 V, TC = 25 C, Charge Pump Current = 600 A, FREF = 52 MHz, Reference Input Divider = 8, Prescale Divider = 8/9, Unless Otherwise Noted)
Parameter Oscillation frequency Reference frequency Phase detector frequency PLL loop bandwidth Output level Output impedance Output VSWR Reference frequency input (FREF) impedance Harmonic suppression Integrated phase noise Single sideband phase noise offset: @ 1 kHz @ 5 kHz @ 10 kHz @ 200 kHz @ 400 kHz @ 600 kHz @ 800 kHz @ 1.8 MHz @6 MHz PLL-reference spurious suppression Frequency settling time Phase settling time Peak phase error Current consumption 120 Within 2 kHz Within 5 deg 250 300 530 5 100 Hz to 100 kHz -91 -90 -90 -127 -140 -145 -148 -153 -165 -100 470 -20 1 Symbol Test Conditions Min 865 13 6.5 25 0 50 *** TBD *** Typical Max 960 52 Units MHz MHz MHz kHz dBm
-
dBc degrees RMS dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc
s s
degrees mA
Note 1: Characterized performance may change if the SKY73100 is configured differently than the test conditions specified here. This characterization used a 6.5 MHz fixed comparison frequency for the PLL phase loop filter. The PLL synthesizer is programmable up to a maximum comparison frequency of 26 MHz but with degraded performance.
Table 6. SKY73100 Spur Suppression Measurements (VCC = 5 V, TC = 25 C, Charge Pump Current = 600 A, FREF = 52 MHz, Reference Input Divider = 8, Prescale Divider = 8/9)
Spurious Power (kHz) 869 881.5 No spur No spur No spur No spur 2272.95 kHz, -100 dBc No spur 894 No spur No spur No spur No spur 2575.45 kHz, -105 dBc No spur Frequency (MHz) 920 No spur No spur No spur No spur 2232.74 kHz, -106 dBc 3615.26 kHz, -107 dBc 9649.31 kHz, -105 dBc 940 No spur No spur No spur No spur No spur 8669.31 kHz, -106 dBc 960 No spur No spur No spur No spur No spur No spur
200 400 600 800 1000 3000
No spur No spur No spur No spur No spur 3366.14 kHz, -107 dBc
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PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
-60 -70 -80 -90 -100
869 MHz 894 MHz 920 MHz 960 MHz
Phase Noise (dBc/Hz)
-110 -120 -130 -140 -150 -160 -170 -180
0.1
1
10
100
1000
10000
100000
S982
Offset Frequency (kHz)
Figure 5. Single Sideband Phase Noise Measurements
20
15
869 MHz 894 MHz 920 MHz 960 MHz
10
Relative Phase degrees)
5
0
-5
-10
-15
-20 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
S983
Time (ms)
Figure 6. Settling Time Measurements
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PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
+5 V From Regulator
C1 10 F
+
C2 10 nF
x 38 37 36 35 34 33 32 31 30
GND
GND
GND
VDD
GND
GND
GND
GND
29
1 2 3
GND GND GND SW_EN GND GND GND GND GND RF_OUT
DATA GND GND GND GND GND CLK N/C
N/C
GND
28
GND
27
N/C
26
x
RF Output Switch Control
4 5 6 7 8 9
GND
25
GND SKY73100
24
GND
23
FREF
22
LD
21
Frequency Reference Lock Detect
x
N/C
20
(50 Controlled Impedance Line)
RF Output
10
GND
LE
19
11
12
13
14 x
15
16
17
18
Latch Enable Data Clock
S1076
Figure 7. SKY73100 Typical Application Schematic
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PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
24X 4.4
4X 3
4X 2
4X 1
2X 1.75
38X SMT Pad
0.1 A B C
Pin 1 Indicator
9
B C
Pin 38
18X 5.9 4X 4.5 4X 3.5 4X 2.5 4X 1.5 4X 0.5
12
C
Pin 1 Indicator See Detail D Pin 1
A
0
2X 1.25 See Detail E 2X 3.75
8X Solder Mask Openings
0.2 A B C
B
A 1.75 0.1
0.15 A B C 0.1
0
Top View
0.5 0.1 (0.1)
Side View
2X (0.1) 0.65 0.1
Bottom View
Metal Pad Edge
0.5 0.05 Metal Pad Edge Solder Mask Edges 0.5 0.1 2X (0.1) Metal Pad Edge 0.65 0.1
0.5 0.1
Detail A
3.375 0.2 x 0.2
Detail B
3.375
Detail C
2.375
Solder Mask Edges
2.375
Solder Mask Edges
All measurements are in millimeters. Dimensioning and tolerancing according to ASME Y14.5M-1994.
Detail D
Detail E
S960
Figure 8. SKY73100 38-Pin MCM Package Dimensions
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PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
1.55 0.05
0.30 0.05 Pin #1 indicator
12.00
4.00
2.00 0.05 1.75 0.10
12.30
B
1.80
1.50 Min.
B
Notes: 1. Carrier tape material: black conductive polystyrene 2. Cover tape material: transparent conductive PSA 3. Cover tape size: 21.3 mm width 4. All measurements are in millimeters
9.35
A
Figure 9. SKY73100 Tape and Reel Dimensions
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24.00 0.30
S961
A
A
11.50 0.05
B
PRELIMINARY DATA SHEET * SKY73100 VCO/SYNTHESIZER
Ordering Information
Model Name SKY73100 865-960 MHz VCO/Synthesizer Manufacturing Part Number SKY73100-11 (Pb-free package) Evaluation Kit Part Number
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200361A * Skyworks Proprietary and Confidential Information * Products and Product Information are Subject to Change Without Notice * June 20, 2007
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